Matti Aarnio's (OH2MQK) ham pages..
SDR DSP components
Earlier I was looking for a way to have a high-quality
sound-card with excellent noise properties, and high-quality
(precission) clock. Since then it has grown to include
the host computer, as Analog's Blackfin DSP can run Linux,
and there are versions with 100 Mbps Ethernet builtin.
Current plan is:
- SDR-DSP-3
- SDR-DSP-IO-IQ-DIFF-2 -- Analog baseband I/Q in and out; signal in differential pairs
- SDR-DSP-IO-IQ-VGA-2 -- Analog baseband I/Q in and out; signal in "VGA" cable coaxials
- SDR-DSP-IO-IF-RXTX -- IF digitizing and producing I/Q
The SDR-DSP-3:
- Analog Devices BlackFin DSP with:
- 16 MB 133 MHz SDRAM (can fit up to 128 MB)
- SPI Flash boot memory
- SPI connected MMC (MultiMediaCard) for simple software update
- Third SPI memory for e.g. non-volatile storage
- Built-in 100 Mbps RJ45 Ethernet
- Running uClinux
- Two plug-on SPORT card slots (custom pinout)
- PC-like ASYNC port for uClinux serial console, but can do also e.g. CAT-commanding of radios.
- A 100x160 mm² 4-layer board
This card can run stand-alone (uC)linux, and do fancy things all by itself,
but it can also be used in dummy mode to act as remote audio card.
The SDR-DSP-IO-IQ-DIFF-2:
- 12.2880 MHz 50 ppm master osc
- Stereo audio DAC with 3rd order LP Bessel filter of corner frequency of 92 kHz; group delay: ~ 2.8 µs; connection is fully differential and DC coupled
- Stereo audio ADC with 3rd order LP Bessel filter of corner frequency of 92 kHz; group delay: ~ 2.8 µs; connection is fully differential and DC coupled
- Two open-collector signals
The SDR-DSP-IO-IQ-VGA-2:
- Incomplete design, but..
- Same as SDR-DSP-IO-IQ-DIFF-2 with single ended signal in and out
- Using same connector pinout (and thus cable) as analog PC video VGA cables use...
The SDR-DSP-IO-IF-RXTX:
- Thoughs only, no complete design yet..
- For RX: AD9874 - IF Digitizing Subsystem (add a VCO.. analogDialogue 37-10 story about VCOs.)
- For TX: AD9857 - CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
The digital upconverter has a problem of not being quite compatible with
DSP I²S (S-Port) protocol, and thus needs some glue logic...
In quadratude mode the AD9874 outputs a load sync pulse, but of course
not anything suitable for serial clock of I²S.
PLL multiplication of load pulse is an option, but required dynamic
range of the frequency is rather large...
Possibility is to use "multichannel framing"..
On mezzanine cards (those SPORT slots), various ideas:
- stereo 24bit ADC and DAC:
- at 96 kHz sample rates, 12.2880 MHz oscillator
- Using stereo signals as I and Q of IQ-modulator/demodulator
- a) Single-ended interface version
- DAC with 92 kHz 3rd order Bessel low-pass filter on output
- ADC without any external active componets on input
- External interface (mis-)using VGA card connector;
plenty of available quality multi-coaxial cables to carry
single-ended baseband signals.
- b) Fully differential interface version
- DAC with 92 kHz 3rd order Bessel low-pass filter on output
- ADC with 92 kHz 3rd order Bessel low-pass filter on input
- External interface (mis-)using shielded RJ45 connector
to carry differential baseband signals.
- An Open Collector PTT driver
- A 78x100 mm² 4-layer card
- c) Full IF digitizing subsystem with
- AD9864/AD9874 IF digitizing subsystem
- IF LO oscillator with exceptional near carrier spectral purity
- e.g. 7th overtone xtal base oscillator with temperature controlled xtal (heated) producing 90-150 MHz reference, which is divided to 45-50 MHz range
- AD9835 produces final reference frequency (10-20 MHz)
- PLL with phase comparator running at 10-20 MHz (ADF4153, ADF4154, ADF4007, ADF4193 ?)
- VCO (Hittite) running at 6.4 GHz (+- 0.1 GHz) ?
- A 2-divider (Hittite) to produce intermediate LO, and a 16-divider (Hittite) producing LO at around 200 MHz
- Additional dividers from LO/intermediate-LO to PLL feedback input (if any needed)
- Final aim is to have LO tunability resolution sub 10 Hz and range around 1 to 2 MHz, and "near" (within 0.4 MHz of the carrier) spectral purity as good as possible
- Preceeding IF input mixers operate at 200 or 500 kHz IF tunability steps with simpler (but equally spectrally demanding) oscillators, possibly a bank of heated 7th order xtals...
- (Studynote: Which is spectrally cleaner: produce PLL reference with DDS, or PLL feedback with DDS division ?)
- Spectrally pure master reference for the AD9864 (derived from IF LO reference ?)
- Something to produce I/Q-modulated output IF ...
- "Stereo" DAC + LPF, differential, DC coupled
- Spectrally pure digital reference for DAC timing
- IF tunability LO (same as above ?)
- I/Q modulator -- ADL5390 ?
- IF band-pass filter ?
- Carrier envelope power detector
- ADC for carrier envelope power signal (for I/Q DC bias tuning)
- A 100x160 mm² 4-layer board with heavy shielding
Eagle CAD material at:
http://ham.zmailer.org/oh2mqk/sdr/
Components:
- Analog (www.analog.com)
- 24 bit 96 kHz 2 channel fdx codecs: AD1839A AD1838A AD1837A AD1835A ADAV803 ADAV801
- 24 bit 96 kHz 4 channel fdx codecs: AD1936A
- DDS (for high precission sample clock adjustment): AD9831 - AD9833
- 12.800000 MHz TCXO master clock for sampler
- Cirrus Logic (www.cirrus.com)
- CS5381: diff input 24 bit 192 kHz stereo ADC (only!), with I2S type serial out datastream
- CS5361: -- little less good version of CS5381
- CS4272: stereo diff in/out 24 bit 192 kHz CODEC; 114 dB dyn, -100 dB THD+N
- CS4271: -- little less good version of CS4272
- CS43122: 24 bit 192 kHz DAC w/ diff out, 122 dB dynamic range, -102 dB THD+N
Other somewhat related (or not) things